Adaptive equalization circuit for magnetic recording channels utilizing signal timing

ABSTRACT

An adaptive equalization circuit for magnetic recording channels which derives an error signal to change the equalizer compensation value from the timing of random signal data and provides continuous feedback compensation.

BACKGROUND OF THE INVENTION

The invention relates to adaptive equalization in magnetic recordingchannels. More particularly the invention concerns an activeequalization circuit which utilizes signal timing of random signal datarather than amplitude to obtain a measure of the needed equalizationsignal.

DISCUSSION OF THE PRIOR ART

The need for equalization or pulse shaping in magnetic recordingchannels is well recognized as being necessary to compensate for signaldistortions that occur due to different head characteristics indifferent machines.

In the past signal equalization was provided by a fixed equalizationcircuit in the channel. However, at higher recording densities now inuse, a single equalization setting is not likely to adequatelycompensate the signal across the total variation that may occur due tohead, media and machine factors.

Other more advanced equalization techniques have been designed includingautomatic equalization loops wherein a training sequence of known pulsesis provided, whereby the loop can measure the amplitude of the knownpulses and determine an error signal that is used to control the amountof the equalization feedback signal necessary to compensate therecording signal. One example of such systems utilizes a so-called twofrequency approach wherein the amplitude is measured at two differentfrequencies and the gain of the compensation circuit is stabilized bysetting the gain at the ratio of the two frequencies to unity. Thiscompensation technique results in ideal compensation at the twofrequencies. However, it has been recognized that distortion occurs atother than the two frequencies sampled, and that the compensationapplied may tend to leave the total pulse envelope in an overcompensated or under compensated state.

Another disadvantage of this type of equalization is that it involves atraining sequence and is therefore not adaptive since it cannot be usedto vary random pulses of a continuing data signal. Also, since atraining sequence is used, such systems are limited to periodiccompensation and not continuous compensation.

Accordingly, a need exists in the art for a continuous equalizationtechnique which can be utilized to derive an error signal from randomdata of a magnetic recording signal.

SUMMARY OF THE INVENTION

An object of the invention is to provide an adaptive equalizationcircuit which utilizes a measurement of signal timing to determine theamount of equalization applied on a continuous basis.

This object and other features of the invention are attained in anequalization circuit which utilizes a feedback compensation path. In thecircuit the relative timing of random data pulses is sensed as anindication of error, the relative timing signal is provided to a logiccircuit and the logic circuit output controls an equalizer amplifier toprovide a variable factor of compensation in accordance with whether thepulse timing is in an over compensated or an under compensated state.The equalization is adaptive in the sense that compensation iscontinuously carried out with respect to the data pulses, and in thesense that random bursts of data pulses are evaluated rather than atraining sequence of known pulse format.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the invention are described in adetailed description included hereinafter, taken in conjunction with thedrawings wherein

FIGS. 1(a) and 1(b) represent typical graphs of under compensation andover compensation with respect to peak shift pulses, and

FIG. 1(c) represents a graph of ideal compensation.

FIG. 2 is a block diagram of the reproduction circuitry of a digitalmagnetic recording channel.

FIG. 3 is a block diagram where the reproduction circuitry of FIG. 2 hasbeen enhanced according to the teaching of this invention.

FIG. 4 is a circuit embodiment used to generate gain control signals inaccordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings, a preferred embodiment of the inventionis described comprising an active symmetrical equalization circuit formagnetic recording channels capable of handling high density signals. Itshould be recognized that the term adaptive equalization is intended tomean compensation of random data without prior knowledge of what thedata is, as opposed to other techniques which use "training sequences"or pulses of known data content to vary the amount of equalization.

FIG. 2 illustrates a block diagram of the reproduction circuitry of adigital magnetic recording channel. Read signals are picked up from themagnetic media (tape or disk) by reproduce head 21. These signals areamplified by amplifier 22 and then shaped by fixed equalizer 23. Datapulser 24 outputs a logic pulse at the time of a positive or negativepeak in the signal on conductor 33. Block 25 is a variable frequencyclock that phase and frequency locks to the logic pulse outputs of datapulser 24. Detector block 26 detects whether the incoming data is a oneor zero using inputs from clock 25, fixed equalizer 23 and data pulser24. The above is all well known and understood in the prior art.

Fixed equalizer 23 is designed to equalize (shape) signals from nominalreproduce heads, media and machines. In high density magnetic recording,these components can vary considerably from their ideal values. Thisresults in under-compensated and/or over-compensated signals such asthose shown in FIGS. 1(a) and 1(b). It is the purpose of this inventionto measure the resulting signal distortion by measuring the variation insignal peak timing and comparing it with the detected data. Thiscomparison is used to generate a correction signal which will increaseor decrease the amount of compensation until a signal substantially likethat of FIG. 1(c) is achieved. When this signal shape is achieved, thesignal peak timing will also be substantially the nominal desired value.

Accordingly, the reproduce circuitry is enhanced by the addition ofcircuitry to measure the signal distortion and a variable equalizer toadjust signal shapes. This arrangement is shown in FIG. 3. Blocks 21a,22a, 23a, 24a, 25a and 26a of FIG. 3 perform substantially the samefunction as do blocks 21, 22, 23, 24, 25 and 26 of FIG. 2, respectively.In FIG. 3, blocks 47, 48, 49 and 69 have been added, in accordance withthe invention. Block 48 is an equalizer filter designed to providenecessary additional compensation. A possible transfer function forblock 48 is: ##EQU1## This is the general equation of a high pass filterdesigned to accentuate high frequencies since high frequency loss is acommon magnetic recording problem. It should be understood that otherfilters may be used in this block. Block 47 is a variable gain amplifierthat varies the amount of signal output to equalizer filter 48. The gainof block 47 is varied in response to the control voltage on conductor65. The value of the control voltage is determined by the measurementsof signal peak timing error which is determined by block 69.

The detailed hardware of block 69 is shown in FIG. 4. It is the purposeof this circuitry to determine the amount of additional equalizationrequired to properly equalize (shape) the read signals so that they willbe substantially like the signals of FIG. 1(c). From the wave forms ofFIG. 1, it can be seen that under-compensated pulses shift away from theclosest neighboring pulses, whereas over-compensated pulses shift towardthe closest neighboring pulses. For the case of ideal compensation,there is substantially zero peak shift.

Based upon this recognition, the logic in Table 1 has been generated for(d, k) run length code, where d is the minimum number of zeroes in thecode and k is the maximum number. In the table T is equal to d+1:

                  TABLE 1                                                         ______________________________________                                                   VALUE OF    VALUE OF                                               SHIFT OF ONE                                                                             BIT AT      BIT AT     COMPEN-                                     AT TIME (N)                                                                              (N-T)       (N+T)      SATION                                      ______________________________________                                        LEFT       1           0          OVER                                        RIGHT      1           0          UNDER                                       RIGHT      0           1          OVER                                        LEFT       0           1          UNDER                                       ______________________________________                                    

In the discussion that follows, D_(N) is defined as the value of the bitdetected at time N; D_(N+T) is defined as the value of the bit at timeN+T for any arbitrary time j or k.

In accordance with the logic of Table 1, a correction will be made attime N only if D_(N) is equal to 1, where D_(N) has possible values of(1, 0).

The logic of Table 1 is based on an assumption that the interference inthe read pulse is reasonably symmetrical and that the read pulse is ofreasonably narrow configuration. This is essentially the function offixed read equalizer 23. Equalizer 23 is designed such that the widestpulse at its output will not be more than two code bits wider than theideally compensated pulse. In general for an arbitrary (d, k) code thepulse width should be less than (4+2d) code bits wide. Thus, for thegraphs of FIG. 1 where d=0, the pulse at the output of fixed equalizer23 should be less than 4 code bits wide.

The logic of Table 1 can be implemented with the detailed hardwareillustrated in FIG. 4. Referring to FIG. 4, block 73 is a clockcorrection circuit that determines if the logic data pulse on conductor68 occurs to the left (prior in time) of the center of the clock periodor to the right (later in time) of the center of the clock period. Theclock wave form is on conductor 55. This circuit function is well knownin the prior art and is used in phase-lock loop designs.

If the logic data pulse on conductor 54 is left shifted, a positivelevel is output on conductor 91. If the logic data pulse is rightshifted, a positive logic level is output on conductor 92. Data is inputon conductor 56 and goes to flip-flop 71. Flip-flops 71, 72, 74 and 75are logic delays and are used to properly time align the input signalsto AND gates 76, 77, 78 and 79, respectively.

The reader will understand that the arrangement of FIG. 4 is for a (d,k) code where d=0. In general for an arbitrary d, k code, each flip-flopblock is replaced by d+1 flip-flops. Thus, for the case shown for d=0,each flip-flop becomes 0+1 or one flip-flop. For a code with d=1, eachflip-flop would be replaced by 1+1 or two flip-flops. In all otherrespects, the circuitry of FIG. 4 would remain the same for all other(d, k) codes.

AND gates 76, 77, 78, 79 and OR gates 80, 81 implement the logic ofTable 1. The output of gate 80 is high if overcompensation is measured.The output of gate 81 is high if under-compensation is measured. Thecircuitry including transistors Ql, Q2, Q3, Q4, Q5, Q6 and resistors R1,R2, R3, R4, R5, R6, R7, R8, R9, R10 form a charge pump. The electriccharge (voltage) on capacitor C1 is increased if the output of gate 80is high representing an over-compensation condition. The voltage oncapacitor C1 is decreased if the output of gate 81 is high representingan under-compensation condition. The voltage on capacitor C1 appears onconductor 65. As seen in FIG. 3, this is used as the control voltage forvariable gain amplifier 47. The gain of amplifier 47 is thus increasedor decreased to correct the measured over or under compensationcondition.

The equalization circuit described hereinbefore is believed to besignificantly different from the prior art in that it is truly adaptive,with the term adaptive being used in the sense that it can adapt even inrandom data without prior knowledge of what that data is. This enablesthe system to equalize the signals being read from tape or disk defectedareas that might otherwise affect data reliability. The technique ofchanging the equalizer in response to an error signal that relates tothe relative timing of present and past detected data values isadvantageous and permits the circuit to be used in a continuouslyadaptive mode in random data. The use of signal timing to effect changesin the equalizer response makes this invention insensitive to signalamplitude loss that occurs in media defects. Thus, the equalized signalis continuously compared with the data to determine whether the amountof equalization is correct.

What is claimed is:
 1. An equalization circuit for a magnetic recordingdata channel which utilizes a feedback compensation path to provide acorrection signal to one input of a summation amplifier, which functionsas an element of a variable equalizer, wherein the amplifier receives amagnetic recording signal as its other input and provides a compensationsignal as the output of the summation amplifier;timing sensing means forsensing the relative timing of random data pulses of the data channeland providing an output signal as an indication of error, logic circuitmeans receiving the timing sensing means output signal and providing anoutput in response thereto for interpreting whether the timing isequivalent to an over compensated or an under compensated state, andcircuit means providing the output of the logic circuit means as thecorrection signal input to vary the compensation signal provided by thesummation amplifier in the feedback compensation path of theequalization circuit.
 2. The equalization circuit of claim 1 wherein thefeedback compensation path operates continually on random date pulses ofthe magnetic recording signal.
 3. The equalization circuit of claim 2further including a fixed equalizer in the data channel.
 4. Theequalization circuit of claim 3 wherein the timing sensing meanscomprises means for detecting three relative levels of timing.
 5. Thecircuit of claim 4 wherein the means provided to receive the output ofthe logic circuit means includes charge pump.
 6. An adaptiveequalization circuit for a magnetic recording channelcomprising:recording channel sensing and amplification means, means forsensing and determining data 1's and data 0's on the channel, timedetection means for continuously monitoring the relative timing ofrandom data pulses on the channel and producing timing signals therefor,logic means receiving the timing signals for determining theinstantaneous compensation state of the data pulses for which timing issensed, signal means receiving the output of the logic means forproviding a control signal, and variable equalizer means forcontinuously varying the equalization of the channel in response to theoutput of the signal means.
 7. The circuit of claim 6 where theequalization means comprises a variable amplifier.
 8. The circuit ofclaim 7 wherein the signal means comprises charge pump means forreceiving the output of the logic means.
 9. The circuit of claim 7wherein the adaptive equalization circuit further includes a fixedequalizer in the recording channel path.
 10. The circuit of claim 8wherein the logic means is responsive to left shift and right shift ofinstantaneous data position.